NCR Corporation has developed a scalable computer system architecture providing more effective scaling of multiprocessor performance than conventional system architectures. The scalable system architecture recognizes and overcomes many limitations of conventional system architectures, such as degradation caused by multiple processors sharing memory and memory busses, and overhead penalties associated with memory/cache coherency.
Key characteristics of this new architecture includes: the use of multiple memory busses to reduce memory bus utilization and physical loading; the use of multi-ported memory to facilitate multiple busses and allow simultaneous use of different memory devices; the use of memory base coherency techniques that significantly reduce coherency overhead; and a symmetric view of system resources by all processors.
One implementation of this architecture employing dual system busses 12 and 14, two dual-ported system memory modules 16 and 18 connected between the two system busses, two processor modules 20 and 22 connected to bus 12, and two processor modules 24 and 26 connected to system bus 14 is shown in FIG. 1. Also shown in FIG. 1 are two Micro Channel input/output (I/O) busses 32 and 42 and interface modules 28 and 30 connecting respective I/O busses 32 and 42 with the system busses.
Each interface module provides a communication pathway between the bus masters residing on the system busses (i.e. memory modules 16 and 18 and processor modules 20, 22, 24 and 26) and the Micro Channel bus units residing on one I/O bus, identified by reference numerals 34, 36, 38, 40, 44, 46 and 48. Arbitration systems are employed to coordinate the use of system busses 12 and 14 and I/O busses 32 and 42. For example,, when a system bus master, such as processor 22, seeks write access to Micro Channel bus unit 36 on I/O bus 32, it must first arbitrate for use of system bus 12. Upon gaining control of bus 12, interface module 28 must then arbitrate for use of I/O bus 32. If I/O bus 32 is available, the request by processor 22 is service immediately.
During normal operation however, there will be times when I/O bus 32 is unavailable or "busy". For example, I/O bus 32 will be unavailable when (1) the bus is owned by one of bus units 34, 36, 38 or 40; (2) an access by a processor on system bus 14 to a bus unit residing on I/O bus 32 is being serviced; (3) a processor on system bus 14 is executing a locked sequence of cycles to an I/O bus 32 bus unit (semaphore operation); or (4) interface module 28 is servicing a previously posted (buffered) write to an I/O bus 32 bus unit by a processor on either system bus 12 or 14.
In a traditional system, once an access to a busy I/O resource is initiated, the target resource would keep the access in an indefinite wait state until the resource became available. Thus in the example above, processor 22, system bus 12 and interface module 28 would be kept in a wait state and unable to perform other transactions until I/O bus 32 became available. Processor 20 would also be prohibited from addressing memory module 16 and 18 and interface module 30. In addition, system deadlock could result in the event that one of processors 20 or 22 requests access to MC I/O bus 32 simultaneously with a request by a Micro Channel bus master for access to system bus 12.